Low noise CMOS image sensor by stack architecture
US10218924B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2017 |
| Grant date | Feb 26, 2019 |
| Priority date | — |
| Expiry date | Apr 12, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/811
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A pixel circuit for use in a high dynamic range (HDR) image sensor includes a photodiode and a floating diffusion is disposed in the first semiconductor wafer. A transfer transistor is disposed in the first semiconductor wafer and is adapted to be switched on to transfer the charge carriers photogenerated in the photodiode to the floating diffusion. An in-pixel capacitor is disposed in a second semiconductor wafer. The first semiconductor wafer is stacked with and coupled to the second semiconductor wafer. A dual floating diffusion (DFD) transistor is disposed in the first semiconductor wafer. The in-pixel capacitor is selectively coupled to the floating diffusion through the DFD transistor. The floating diffusion is set to low conversion gain in response to the in-pixel capacitor being coupled to the floating diffusion, and high conversion gain in response to the in-pixel capacitor being decoupled from the floating diffusion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.