Patent · US Active

Securing access to integrated circuit scan mode and data

US10222417B1 · kind B1 · utility

3Cited by

12References

17Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Akhil Garg · Sidhauli, IN
Dale Edward Meehl · Melbourne, US
Sahil Jain · Ghaziabad, IN

Key dates

Filing date	Nov 28, 2016
Grant date	Mar 5, 2019
Priority date	—
Expiry date	Apr 14, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH04L2209/26
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Embodiments relate to providing security of scan mode access and data in an integrated circuit. In embodiments, one or both of two layers of security are provided. A first layer includes requiring a complex initialization sequence to be performed in order to access scan mode. A second layer includes scrambling the scan data before it is output from the circuit under test, which prevents unauthorized persons from extracting useful information from the output scan data. Further embodiments relate to methodologies for utilizing these protection layers after manufacture of the integrated circuit and incorporating these protection layers in an integrated circuit design flow.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.