Method and system for efficient cache buffering supporting variable stripe sizes to enable hardware acceleration
US10223009B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2016 |
| Grant date | Mar 5, 2019 |
| Priority date | — |
| Expiry date | Oct 26, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for efficient cache buffering are provided. The disclosed method includes receiving an Input/Output (I/O) command from a host system at a storage controller, parsing the I/O command at the storage controller with a host I/O manager to extract command instructions therefrom. The host I/O manager is able to generate at least one local message that includes the command instructions extracted from the I/O command and transmit the at least one local message to a cache manager. The cache manager is enabled to work in local memory to execute the command instructions contained in the at least one message. The cache manager is also configured to chain multiple buffer segments together on-demand to support multiple stripe sizes that are specific to the I/O command received from the host system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.