Horia Simionescu
49Patents
4h-index
63Co-inventors
66Inventor score
Filing activity: Jun 7, 1999 → Dec 5, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7082494B1 | Disk drive executing a preemptive multitasking operating system comprising tasks of varying priority | Physics | 187 | Expired |
| US6141728A | Embedded cache manager | Physics | 48 | Expired |
| US9256384B2 | Method and system for reducing write latency in a data storage system by using a command-push model | Physics | 8 | Active |
| US9841902B2 | Peripheral component interconnect express controllers configured with non-volatile memory express interfaces | Physics | 4 | Active |
| US9524107B2 | Host-based device drivers for enhancing operations in redundant array of independent disks systems | Physics | 4 | Active |
| US9542101B2 | System and methods for performing embedded full-stripe write operations to a data volume with data elements distributed across multiple modules | Physics | 3 | Active |
| US9058274B2 | System and method of selective READ cache retention for a rebooted node of a multiple-node storage cluster | Emerging Cross-Sectional Technologies | 2 | Active |
| US9015525B2 | Smart active-active high availability DAS systems | Physics | 2 | Active |
| US10169232B2 | Associative and atomic write-back caching system and method for storage subsystem | Physics | 2 | Active |
| US9292204B2 | System and method of rebuilding READ cache for a rebooted node of a multiple-node storage cluster | Physics | 2 | Active |
| US10223009B2 | Method and system for efficient cache buffering supporting variable stripe sizes to enable hardware acceleration | Physics | 1 | Active |
| US9965397B2 | Fast read in write-back cached memory | Physics | 1 | Active |
| US10649906B2 | Method and system for hardware accelerated row lock for a write back volume | Physics | 1 | Active |
| US9292228B2 | Selective raid protection for cache memory | Physics | 1 | Active |
| US11169920B2 | Cache operations in a hybrid dual in-line memory module | Physics | 1 | Active |
| US9734062B2 | System and methods for caching a small size I/O to improve caching device endurance | Physics | 1 | Active |
| US10282301B2 | Method and system for hardware accelerated read-ahead caching | Physics | 1 | Active |
| US9286175B2 | System and method of write hole protection for a multiple-node storage cluster | Physics | 1 | Active |
| US9158695B2 | System for dynamically adaptive caching | Physics | 1 | Active |
| US9274713B2 | Device driver, method and computer-readable medium for dynamically configuring a storage controller based on RAID type, data alignment with a characteristic of storage elements and queue depth in a cache | Physics | 1 | Active |
| US10423357B2 | Devices and methods for managing memory buffers | Physics | 1 | Active |
| US10929056B2 | Interruption of program operations at a memory sub-system | Physics | 0 | Active |
| US12066949B2 | Address translation based on page identifier and queue identifier | Physics | 0 | Active |
| US11531622B2 | Managing data dependencies for out of order processing in a hybrid DIMM | Physics | 0 | Active |
| US11698876B2 | Quality of service control of logical devices for a memory sub-system | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.