Partially and fully parallel normaliser
US10223068B2 · kind B2 · utility
6Cited by
3References
14Claims
0Family size
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Key dates
| Filing date | Jun 28, 2017 |
| Grant date | Mar 5, 2019 |
| Priority date | — |
| Expiry date | Jun 28, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2205/003
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Hardware logic arranged to normalize (or renormalize) an n-bit input number is described in which at least a proportion of a left shifting operation is performed in parallel with a leading zero count operation. In various embodiments the left shifting and the leading zero count are performed independently. In various other embodiments, a subset of the bits output by a leading zero counter are input to a left shifter and the output from the left shifter is input to a renormalization block which completes the remainder of the left shifting operation independently of any further input from the leading zero counter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.