Theo Alan Drane
39Patents
3h-index
13Co-inventors
60Inventor score
Filing activity: Jun 14, 2004 → Nov 17, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9703525B2 | Partially and fully parallel normaliser | Physics | 7 | Active |
| US10223068B2 | Partially and fully parallel normaliser | Physics | 6 | Active |
| US10977000B2 | Partially and fully parallel normaliser | Physics | 3 | Active |
| US10698655B2 | Partially and fully parallel normaliser | Physics | 3 | Active |
| US8943447B2 | Method and apparatus for synthesising a sum of addends operation and an integrated circuit | Physics | 2 | Active |
| US8862652B2 | Method and apparatus for performing lossy integer multiplier synthesis | Physics | 2 | Active |
| US8381154B2 | Method of making apparatus for computing multiple sum of products | Physics | 2 | Active |
| US7822138B2 | Calculating apparatus and method for use in a maximum likelihood detector and/or decoder | Electricity | 1 | Active |
| US8527924B2 | Method and apparatus for performing formal verification of polynomial datapath | Physics | 1 | Active |
| US12169700B2 | Method and apparatus for use in the design and manufacture of integrated circuits | Physics | 0 | Active |
| US10331405B2 | Evaluating polynomials in hardware logic | Physics | 0 | Active |
| US12353862B2 | Automatic code generation of optimized RTL via redundant code removal | Physics | 0 | Active |
| US10185545B2 | Trailing or leading zero counter having parallel and combinational logic | Physics | 0 | Active |
| US9830131B2 | Trailing or leading zero counter having parallel and combinational logic | Physics | 0 | Active |
| US10296293B2 | Low-area fixed-point polynomials | Physics | 0 | Active |
| US10175943B2 | Sorting numbers in hardware | Electricity | 0 | Active |
| US10606558B2 | Error bounded multiplication by invariant rationals | Physics | 0 | Active |
| US12141548B2 | Trailing or leading digit anticipator | Physics | 0 | Active |
| US10162600B2 | Method and apparatus for use in the design and manufacture of integrated circuits | Physics | 0 | Active |
| US12079590B2 | Efficient dual-path floating-point arithmetic operators | Electricity | 0 | Active |
| US10698660B2 | Trailing or leading digit anticipator | Physics | 0 | Active |
| US11809795B2 | Implementing fixed-point polynomials in hardware logic | Physics | 0 | Active |
| US11748060B2 | Method and apparatus for use in the design and manufacture of integrated circuits | Physics | 0 | Active |
| US11861323B2 | Partially and fully parallel normaliser | Physics | 0 | Active |
| US10540141B2 | Method and apparatus for use in the design and manufacture of integrated circuits | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.