Linkable issue queue parallel execution slice processing method
US10223125B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2018 |
| Grant date | Mar 5, 2019 |
| Priority date | — |
| Expiry date | Jul 30, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3891
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An execution slice circuit for a processor core has multiple parallel instruction execution slices and provides flexible and efficient use of internal resources. The execution slice circuit includes a master execution slice for receiving instructions of a first instruction stream and a slave execution slice for receiving instructions of a second instruction stream and instructions of the first instruction stream that require an execution width greater than a width of the slices. The execution slice circuit also includes a control logic that detects when a first instruction of the first instruction stream has the greater width and controls the slave execution slice to reserve a first issue cycle for issuing the first instruction in parallel across the master execution slice and the slave execution slice.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.