Managing virtual-address caches for multiple memory page sizes
US10223279B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2016 |
| Grant date | Mar 5, 2019 |
| Priority date | — |
| Expiry date | Mar 8, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/683
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A translation lookaside buffer stores information indicating respective page sizes for different translations. A virtual-address cache module manages entries, where each entry stores a memory block in association with a virtual address and a code representing at least one page size of a memory page on which the memory block is located. The managing includes: receiving a translation lookaside buffer invalidation instruction for invalidating at least one translation lookaside buffer entry in the translation lookaside buffer, where the translation lookaside buffer invalidation instruction includes at least one invalid virtual address; comparing selected bits of the invalid virtual address with selected bits of each of a plurality of virtual addresses associated with respective entries in the virtual-address cache module, based on the codes; and invalidating one or more entries in the virtual-address cache module based on the comparing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.