Inventor · Marlborough, MA, US

Michael Bertone

37Patents
11h-index
27Co-inventors
75Inventor score

Filing activity: Aug 31, 2000 → Nov 22, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US7535907B2 TCP engine Electricity 56 Active
US6622225B1 System for minimizing memory bank conflicts in a computer system Physics 49 Expired
US7213087B1 Mechanism to control the allocation of an N-source shared buffer Electricity 35 Expired
US6754739B1 Computer resource management and allocation system Physics 32 Expired
US6654858B1 Method for reducing directory writes and latency in a high performance, directory-based, coherency protocol Physics 24 Expired
US9208103B2 Translation bypass in multi-stage address translation Physics 19 Active
US6546465B1 Chaining directory reads and writes to reduce DRAM bandwidth in a directory based CC-NUMA protocol Physics 17 Expired
US7099913B1 Speculative directory writes in a directory based cache coherent nonuniform memory access protocol Physics 13 Expired
US9268694B2 Maintenance of cache and tags in a translation lookaside buffer Physics 12 Active
US9639476B2 Merged TLB structure for multiple sequential address translations Physics 12 Active
US6662265B1 Mechanism to track all open pages in a DRAM memory system Physics 11 Expired
US11176055B1 Managing potential faults for speculative page table access Physics 11 Active
US9645941B2 Collapsed address translation with multiple page sizes Physics 9 Active
US8977944B2 DRAM address protection Electricity 4 Active
US9501243B2 Method and apparatus for supporting wide operations using atomic sequences Physics 3 Active
US10817300B2 Managing commit order for an external instruction relative to two unissued queued instructions Physics 2 Active
US9753859B2 Input output value prediction with physical or virtual addressing for virtual environment Physics 2 Active
US10223279B2 Managing virtual-address caches for multiple memory page sizes Physics 2 Active
US10599577B2 Admission control for memory access requests Physics 2 Active
US11507379B2 Managing load and store instructions for memory barrier handling Physics 1 Active
US9323715B2 Method and apparatus to represent a processor context with fewer bits Physics 1 Active
US10846239B2 Managing translation lookaside buffer entries based on associativity and page size Physics 1 Active
US9390023B2 Method and apparatus for conditional storing of data using a compare-and-swap based approach Physics 1 Active
US11573800B2 Complex I/O value prediction for multiple values with physical or virtual addresses Physics 1 Active
US10331500B2 Managing fairness for lock and unlock operations using operation prioritization Physics 1 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.