Flexible I/O DMA address allocation in virtualized systems
US10223284B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2015 |
| Grant date | Mar 5, 2019 |
| Priority date | — |
| Expiry date | Jul 14, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2009/45583
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system can translate an input/output (I/O) direct memory access (DMA) address to a physical system memory address in a data processing system. In response to receiving a DMA packet containing a requester identity (RID) associated with a partitionable endpoint (PE) number and an I/O DMA address, the system can retrieve an entry associated with the RID from a first translation validation table (TVT). Using that entry, the system can validate the number of TVT entries and extract from the I/O DMA address an offset. This offset can be validated and used to retrieve an entry in a second TVT. Data from this entry can be validated and the system can use this to access another table to retrieve the translation to the physical system memory address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.