Placement clustering-based white space reservation
US10223489B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2016 |
| Grant date | Mar 5, 2019 |
| Priority date | — |
| Expiry date | Nov 30, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method place unit-level components in a macro within a unit of an integrated circuit that includes two or more of the units that each include two or more of the macros. The method includes detecting white space in a congestion plot of the macro. The white space represents potential placement areas for the unit-level components. The method also includes performing wire reach analysis between sources and sinks on different sides of the macro to determine an allowable region for the unit-level components, and deriving a buffer and latch placement reservation area in which to place the unit-level components based on the white space and the allowable region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.