Inventor · Balingen, DE

Harry Barowski

60Patents
9h-index
59Co-inventors
81Inventor score

Filing activity: May 24, 2001 → Jun 16, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US7694112B2 Multiplexing output from second execution unit add/saturation processing portion of wider width intermediate result of first primitive execution unit for compound computation Physics 38 Active
US9501603B2 Integrated circuit design changes using through-silicon vias Physics 37 Active
US6968476B2 Checkpointing a superscalar, out-of-order processor for error recovery Physics 26 Expired
US8375345B1 Soft-bounded hierarchical synthesis Physics 18 Active
US8245065B2 Power gating processor execution units when number of instructions issued per cycle falls below threshold and are independent until instruction queue is full Physics 16 Active
US8427833B2 Thermal power plane for integrated circuits Emerging Cross-Sectional Technologies 12 Active
US9406375B1 Write address synchronization in 2 read/1write SRAM arrays Physics 12 Active
US7502918B1 Method and system for data dependent performance increment and power reduction Physics 9 Active
US6986027B2 Universal load address/value prediction using stride-based pattern history and last-value prediction in a two-level table scheme Physics 9 Expired
US8316335B2 Multistage, hybrid synthesis processing facilitating integrated circuit layout Physics 9 Active
US8253234B2 Optimized semiconductor packaging in a three-dimensional stack Electricity 8 Active
US7509511B1 Reducing register file leakage current within a processor Emerging Cross-Sectional Technologies 7 Active
US8805132B2 Integrated circuit package connected to a data transmission medium Electricity 6 Active
US7849428B2 Formally deriving a minimal clock-gating scheme Physics 5 Active
US8578196B2 Zero indication forwarding for floating point unit power reduction Emerging Cross-Sectional Technologies 4 Active
US8476112B2 Optimized semiconductor packaging in a three-dimensional stack Electricity 4 Active
US9910948B2 Layout of large block synthesis blocks in integrated circuits Physics 3 Active
US9928329B2 Layout of large block synthesis blocks in integrated circuits Physics 3 Active
US8405998B2 Heat sink integrated power delivery and distribution for integrated circuits Emerging Cross-Sectional Technologies 3 Active
US8989532B2 Integrated circuit package connected to an optical data transmission medium using a coolant Physics 3 Active
US8421500B2 Integrated circuit with stacked computational units and configurable through vias Electricity 3 Active
US11501196B2 Qubit tuning by magnetic fields in superconductors Electricity 2 Active
US8255726B2 Zero indication forwarding for floating point unit power reduction Emerging Cross-Sectional Technologies 2 Active
US10079070B2 Testing content addressable memory and random access memory Physics 1 Active
US10593420B2 Testing content addressable memory and random access memory Physics 1 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.