Method and apparatus for enhancing read stability of a static random access memory circuit in low voltage operation
US10224097B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2018 |
| Grant date | Mar 5, 2019 |
| Priority date | — |
| Expiry date | Mar 1, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/145
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Read stability of a memory is enhanced in low voltage operation mode by selectively boosting a cell supply voltage for a row of memory cells. The boosted voltage results from a capacitive coupling to the word line in that row. The capacitive coupling is implemented by running the metal line of the power supply line for the cell supply voltage and the metal line for the word line adjacent to each other in a common metallization level. The selective voltage boost is controlled in response to operation of a modified memory cell exhibiting a deteriorated write margin. An output of the modified memory cell is compared to a threshold to generate a signal for controlling the selective voltage boost. Word line under-voltage circuitry is further provided to control application of an under-voltage to the word line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.