Kedar Janardan Dhori
22Patents
3h-index
18Co-inventors
56Inventor score
Filing activity: Dec 30, 2008 → Oct 12, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9865333B2 | Temperature compensated read assist circuit for a static random access memory (SRAM) | Physics | 5 | Active |
| US9685209B1 | Circuit for generating a sense amplifier enable signal with variable timing | Physics | 3 | Active |
| US9940997B2 | Method and apparatus for enhancing read stability of a static random access memory circuit in low voltage operation | Physics | 3 | Active |
| US8154936B2 | Single-ended bit line based storage system | Physics | 1 | Active |
| US11984151B2 | Adaptive bit line overdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Physics | 1 | Active |
| US12087356B2 | Serial word line actuation with linked source voltage supply modulation for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Physics | 1 | Active |
| US12406705B2 | In-memory computation circuit using static random access memory (SRAM) array segmentation | Physics | 0 | Active |
| US9208040B2 | Repair control logic for safe memories having redundant elements | Physics | 0 | Active |
| US12353341B2 | Tuning of read/write cycle time delay for a memory circuit dependent on operational mode selection | Physics | 0 | Active |
| US12176025B2 | Adaptive body bias management for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Physics | 0 | Active |
| US12183424B2 | Bit-cell architecture based in-memory compute | Physics | 0 | Active |
| US12400707B2 | Device and method for reading data from memory cells | Physics | 0 | Active |
| US12328858B2 | Silicon-on-insulator semiconductor device with a static random access memory circuit | Electricity | 0 | Active |
| US11758707B2 | SRAM cell layout including arrangement of multiple active regions and multiple gate regions | Electricity | 0 | Active |
| US12165698B2 | Circuitry for adjusting retention voltage of a static random access memory (SRAM) | Physics | 0 | Active |
| US12361982B2 | Memory architecture supporting both conventional memory access mode and digital in-memory computation processing mode | Physics | 0 | Active |
| US12292780B2 | Computing system power management device, system and method | Physics | 0 | Active |
| US12237007B2 | Selective bit line clamping control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Physics | 0 | Active |
| US12170120B2 | Built-in self test circuit for segmented static random access memory (SRAM) array input/output | Physics | 0 | Active |
| US12354644B2 | Adaptive word line underdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Physics | 0 | Active |
| US11726543B2 | Computing system power management device, system and method | Physics | 0 | Active |
| US10224097B2 | Method and apparatus for enhancing read stability of a static random access memory circuit in low voltage operation | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.