Method, system and device for error correction in reading memory devices
US10224099B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2018 |
| Grant date | Mar 5, 2019 |
| Priority date | — |
| Expiry date | Feb 6, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are devices and methods for storing values, symbols, parameters or conditions in memory devices as states, and subsequently mapping detected states as values, symbols parameters or conditions. In one implementation write operations may place first and second memory elements in a particular impedance state selected from between a low impedance or conductive state and a high impedance or insulative state. The high impedance or insulative state represents a first binary value or symbol while the low high impedance or conductive state represents a second binary value or symbol. Subsequently detected impedance states of the first and second memory elements may be mapped to the second binary value or symbol responsive to either of the detected impedance states being the high impedance or insulative state and the second detected impedance state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.