Emre Ozer
46Patents
8h-index
28Co-inventors
71Inventor score
Filing activity: Sep 13, 2005 → Jan 24, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7937535B2 | Managing cache coherency in a data processing apparatus | Emerging Cross-Sectional Technologies | 427 | Active |
| US8099556B2 | Cache miss detection in a data processing apparatus | Physics | 42 | Active |
| US10607147B2 | Estimating a number of occupants in a region | Physics | 39 | Active |
| US7707390B2 | Instruction issue control within a multi-threaded in-order superscalar processor | Physics | 28 | Active |
| US8694862B2 | Data processing apparatus using implicit data storage data storage and method of implicit data storage | Electricity | 15 | Active |
| US7769955B2 | Multiple thread instruction fetch from different cache levels | Physics | 12 | Active |
| US7805595B2 | Data processing apparatus and method for updating prediction data based on an operation's priority level | Physics | 12 | Active |
| US8205206B2 | Data processing apparatus and method for managing multiple program threads executed by processing circuitry | Physics | 11 | Active |
| US7895469B2 | Integrated circuit using speculative execution | Physics | 7 | Active |
| US8621272B2 | Integrated circuit with error repair and fault tolerance | Physics | 7 | Active |
| US8195886B2 | Data processing apparatus and method for implementing a replacement scheme for entries of a storage unit | Physics | 6 | Active |
| US9269418B2 | Apparatus and method for controlling refreshing of data in a DRAM | Physics | 5 | Active |
| US7979642B2 | Managing the storage of high-priority storage items in storage units in multi-core and multi-threaded systems using history storage and control circuitry | Physics | 4 | Active |
| US8732523B2 | Data processing apparatus and method for analysing transient faults occurring within storage elements of the data processing apparatus | Physics | 3 | Active |
| US10628277B2 | Device, system and process for redundant processor error detection | Physics | 1 | Active |
| US9519538B2 | Error recovery following speculative execution with an instruction processing pipeline | Physics | 1 | Active |
| US9032188B2 | Issue policy control within a multi-threaded in-order superscalar processor | Physics | 1 | Active |
| US11953387B2 | Circuitry fabricated on a flexible substrate | Electricity | 1 | Active |
| US8826097B2 | Memory scrubbing | Electricity | 1 | Active |
| US9116844B2 | Data processing apparatus and method for analysing transient faults occurring within storage elements of the data processing apparatus | Physics | 1 | Active |
| US10303566B2 | Apparatus and method for checking output data during redundant execution of instructions | Physics | 1 | Active |
| US10224099B1 | Method, system and device for error correction in reading memory devices | Physics | 1 | Active |
| US12343308B2 | Packaging for a pharmaceutical product | Performing Operations; Transporting | 0 | Active |
| US10289332B2 | Apparatus and method for increasing resilience to faults | Physics | 0 | Active |
| US12188786B2 | Energy efficient smart label with an electrically destructible fuse | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.