Element place on laminates
US10224269B2 · kind B2 · utility
0Cited by
9References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2015 |
| Grant date | Mar 5, 2019 |
| Priority date | — |
| Expiry date | Dec 17, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A module includes a laminate, the laminate including a solder mask layer and at least one depression in an upper surface of the solder mask layer that does not pass all of the way through the solder mask layer. The module also includes a first electronic element disposed in a first of the at least one depressions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.