Inventor · Lagrangeville, NY, US

Brian M. Erwin

31Patents
4h-index
37Co-inventors
59Inventor score

Filing activity: Apr 30, 2010 → Mar 12, 2020

Most-cited inventions

PatentTitleAreaCited byStatus
US9401336B2 Dual layer stack for contact formation Electricity 48 Active
US9997424B2 Method of forming a temporary test structure for device fabrication Electricity 17 Active
US9324669B2 Use of electrolytic plating to control solder wetting Electricity 4 Active
US9565777B1 Security mesh and method of making Electricity 4 Active
US9601423B1 Under die surface mounted electrical elements Electricity 4 Active
US8563416B2 Coaxial solder bump support structure Electricity 4 Active
US8710656B2 Redistribution layer (RDL) with variable offset bumps Electricity 3 Active
US9735071B2 Method of forming a temporary test structure for device fabrication Electricity 3 Active
US10756041B1 Finned contact Electricity 2 Active
US9190376B1 Organic coating to inhibit solder wetting on pillar sidewalls Electricity 2 Active
US10043723B2 Method of forming a temporary test structure for device fabrication Electricity 1 Active
US8686749B2 Thermal interface material, test structure and method of use Electricity 1 Active
US10840214B2 Carrier and integrated memory Electricity 0 Active
US10892249B2 Carrier and integrated memory Electricity 0 Active
US9728440B2 Non-transparent microelectronic grade glass as a substrate, temporary carrier or wafer Electricity 0 Active
US9640492B1 Laminate warpage control Electricity 0 Active
US10431563B1 Carrier and integrated memory Electricity 0 Active
US10224269B2 Element place on laminates Electricity 0 Active
US9748135B2 Substrate including selectively formed barrier layer Electricity 0 Active
US11009545B2 Integrated circuit tester probe contact liner Physics 0 Active
US9343420B2 Universal solder joints for 3D packaging Electricity 0 Active
US9754823B2 Substrate including selectively formed barrier layer Electricity 0 Active
US9899280B2 Method of forming a temporary test structure for device fabrication Electricity 0 Active
US10515929B2 Carrier and integrated memory Electricity 0 Active
US11168400B2 Formation of terminal metallurgy on laminates and boards Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.