Sintered solder for fine pitch first-level interconnect (FLI) applications
US10224299B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2016 |
| Grant date | Mar 5, 2019 |
| Priority date | — |
| Expiry date | Dec 29, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3841
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Foundation layers and methods of forming a foundation layer are described. Die pads are formed over a die. A dielectric layer is formed over die pads and the die. The dielectric layer is then recessed to expose top portions of the die pads. A first plurality of sintered conductive vias are formed over the die pads. The first sintered conductive vias are coupled to at least one of the die pads. In addition, a photoresist layer may be formed over the dielectric layer and the top portions of the die pads. Via openings are formed in the photoresist layer. A second plurality of sintered conductive vias may then be formed over the first sintered conductive vias to form a plurality of sintered conductive lines. Each of the first and second sintered conductive vias are formed with a liquid phase sintering (LPS) solder paste.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.