Isolation structure for semiconductor device having self-biasing buried layer and method therefor

US10224323B2 · kind B2 · utility

Assignee

• SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC · US

Inventors

• Moshe Agam · Portland, US
• Johan Camiel Julia Janssens · Asse, BE
• Jaroslav Pjencak · Dolní Bečva, CZ
• Thierry Coffi Herve Yao · Portland, US
• Mark Griswold · Chandler, US
• Weize Chen · Phoenix, US

Key dates

• Filing date: Aug 4, 2017
• Grant date: Mar 5, 2019
• Expiry date: Aug 26, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/393
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor device includes a floating buried doped region, a first doped region disposed between the floating buried doped region and a first major surface, and a semiconductor region disposed between the floating buried doped region and a second major surface. A trench isolation structure extends from the first major surface and terminates within the semiconductor region and the floating buried doped region abuts the trench isolation structure. A second doped region is disposed in the first doped region has an opposite conductivity type to the first doped region. A first isolation device is disposed in the first doped region and is configured to divert current injected into the semiconductor device from other regions thereby delaying the triggering of an internal SCR structure. In one embodiment, a second isolation structure is disposed within the first doped region and is configured to disrupt a leakage path along a sidewall surface of the trench isolation structure.