Three-dimensional memory device with vertical bit lines and replacement word lines and method of making thereof
US10224372B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 24, 2017 |
| Grant date | Mar 5, 2019 |
| Priority date | — |
| Expiry date | May 24, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
Abstract
A method of forming a device includes forming an in-process alternating stack of insulating layers and sacrificial material layers over a substrate, forming sacrificial pillar structures through the in-process alternating stack, where the sacrificial pillar structures are arranged in rows, forming inter-pillar cavities between each neighboring pair of sacrificial pillar structures, forming dielectric bridge structures by depositing a dielectric fill material in the inter-pillar cavities, selectively removing the sacrificial pillar structures to form pillar cavities, replacing remaining portions of the sacrificial material layers with electrically conductive layers through the pillar cavities, and forming pillar structures in the pillar cavities, where each of the pillar structures includes a respective vertical electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.