PCB based semiconductor package with impedance matching network elements integrated therein
US10225922B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2016 |
| Grant date | Mar 5, 2019 |
| Priority date | — |
| Expiry date | Oct 27, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/049
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a metal baseplate having a die attach region and a peripheral region, a transistor die having a reference terminal attached to the die attach region and an RF terminal facing away from the baseplate, and a multilayer circuit board having a first side attached to the peripheral region and a second side facing away from the baseplate. The multilayer circuit board includes two embedded electrically conductive layers that are separated from the first and second sides by layers of composite fiber, and an embedded dielectric layer disposed between the two embedded electrically conductive layers. The embedded dielectric layer has a higher dielectric constant than the layers of composite fiber.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.