Clock selection circuit and test clock generation circuit for LBIST and ATPG test circuit

US10228420B2 · kind B2 · utility

Assignee

• STMicroelectronics International N.V. · NL

Inventors

• Venkata Narayanan Srinivasan · Greater Noida, IN
• Nimit Endlay · Greater Noida, IN
• Balwinder Singh Soni · Faridabad, IN

Key dates

• Filing date: Sep 19, 2016
• Grant date: Mar 12, 2019
• Expiry date: Jan 26, 2037

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F11/27
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A test circuit receives LBIST and ATPG mode signals, and generates a first output as high when in ATPG or LBIST, and a second output as low when in ATPG or LBIST. A multiplexing circuit receives an ATPG clock and functional clock, and outputs one. A clock gate circuit includes a first latch receiving the second output, and an enable input receiving an inverse of the ATPG clock or functional clock. A second latch receives the first output, and has an enable input receiving the inverse of the ATPG clock or functional clock. The clock gate circuit includes a first AND gate receiving output of the first latch and ATPG clock or functional clock, a second AND gate receiving output of the second latch and the ATPG clock or LBIST clock, and an OR gate receiving outputs of the first and second AND gates, and generating a test clock.