Inventor · Greater Noida, IN

Venkata Narayanan Srinivasan

36Patents
4h-index
19Co-inventors
56Inventor score

Filing activity: Jun 29, 2011 → May 13, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US9698771B1 Testing of power on reset (POR) and unmaskable voltage monitors Electricity 10 Active
US10802077B1 Test circuit for dynamic checking for faults on functional and BIST clock paths to memory in both ATPG and LBIST modes Physics 6 Active
US11119153B1 Isolation enable test coverage for multiple power domains Physics 5 Active
US9941875B2 Testing of power on reset (POR) and unmaskable voltage monitors Electricity 4 Active
US10502784B2 Voltage level monitoring of an integrated circuit for production test and debug Electricity 3 Active
US9335375B2 Integrated device test circuits and methods Electricity 3 Active
US10996266B2 System and method for testing voltage monitors Physics 3 Active
US10228420B2 Clock selection circuit and test clock generation circuit for LBIST and ATPG test circuit Physics 2 Active
US11513544B1 Reset and safe state logic generation in dual power flow devices Electricity 2 Active
US11340292B2 System and method for parallel testing of electronic device Physics 2 Active
US10151797B2 Logic built-in self-test (LBIST) with pipeline scan enable launch on shift (LOS) flip-flop circuit Physics 2 Active
US11714131B1 Circuit and method for scan testing Physics 2 Active
US10393804B2 Clock selection circuit and test clock generation circuit for LBIST and ATPG test circuit Physics 2 Active
US10747282B2 Test circuit for electronic device permitting interface control between two supply stacks in a production test of the electronic device Electricity 2 Active
US11442108B1 Isolation logic test circuit and associated test method Physics 2 Active
US11726140B2 Scan circuit and method Physics 1 Active
US11550348B2 Methods and devices for bypassing a voltage regulator Emerging Cross-Sectional Technologies 1 Active
US10386411B2 Sequential test access port selection in a JTAG interface Physics 1 Active
US10527672B2 Voltage regulator bypass circuitry usable during device testing operations Electricity 1 Active
US11983025B2 Reset and safe state logic generation in dual power flow devices Physics 0 Active
US11041905B2 Combinatorial serial and parallel test access port selection in a JTAG interface Physics 0 Active
US12366605B2 Area, cost, and time-effective scan coverage improvement Physics 0 Active
US11557364B1 ATPG testing method for latch based memories, for area reduction Electricity 0 Active
US12020760B2 ATPG testing method for latch based memories, for area reduction Electricity 0 Active
US12399218B2 PORs testing in multiple power domain devices Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.