Processors, methods, and systems to access a set of registers as either a plurality of smaller registers or a combined larger register
US10228941B2 · kind B2 · utility
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30Claims
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Key dates
| Filing date | Jun 28, 2013 |
| Grant date | Mar 12, 2019 |
| Priority date | — |
| Expiry date | Jan 20, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30192
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor of an aspect includes a set of registers capable of storing packed data. An execution unit is coupled with the set of registers. The execution unit is to access the set of registers in at least two different ways in response to instructions. The at least two different ways include a first way in which the set of registers are to represent a plurality of N-bit registers. The at least two different ways also include a second way in which the set of registers are to represent a single register of at least 2N-bits. In one aspect, the at least 2N-bits is to be at least 256-bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.