Method and apparatus for avoiding bus contention after initialization failure
US10229057B2 · kind B2 · utility
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17Claims
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Key dates
| Filing date | Sep 30, 2016 |
| Grant date | Mar 12, 2019 |
| Priority date | — |
| Expiry date | Nov 9, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, an apparatus comprises a storage device comprising a NAND flash memory device comprising a plurality of NAND flash memory units. The storage device is to determine that the NAND flash memory device did not pass an initialization procedure; identify a first addressing scheme that is implemented by one or more of the NAND flash memory units that initialized properly; and after the initialization procedure, instruct each of the plurality of NAND flash memory units to implement the first addressing scheme.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.