Bharat Pathak
17Patents
7h-index
30Co-inventors
66Inventor score
Filing activity: Apr 11, 1997 → Jun 24, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5944837A | Controlling flash memory program and erase pulses | Physics | 40 | Expired |
| US5907700A | Controlling flash memory program and erase pulses | Physics | 24 | Expired |
| US5896338A | Input/output power supply detection scheme for flash memory | Physics | 15 | Expired |
| US7664337B2 | Film grain generation and addition | Physics | 14 | Active |
| US8340185B2 | Systems and methods for a motion compensated picture rate converter | Electricity | 11 | Active |
| US7821578B2 | Reconfigurable self-calibrating adaptive noise reducer | Physics | 8 | Active |
| US6449211B1 | Voltage driver for a memory | Physics | 7 | Expired |
| US7889940B2 | Film grain generation and addition | Physics | 4 | Active |
| US8175405B1 | Adaptive MPEG noise reducer | Electricity | 3 | Active |
| US10438656B2 | System and method for performing a concurrent multiple page read of a memory array | Physics | 2 | Active |
| US7623721B1 | High-speed dithering architecture | Physics | 1 | Active |
| US6747630B2 | Method to up-sample frequency rich images without significant loss of image sharpness | Physics | 1 | Expired |
| US9008455B1 | Adaptive MPEG noise reducer | Electricity | 0 | Active |
| US12334136B2 | Independent multi-page read operation enhancement technology | Physics | 0 | Active |
| US7933461B1 | High-speed dithering architecture | Physics | 0 | Active |
| US10229057B2 | Method and apparatus for avoiding bus contention after initialization failure | Physics | 0 | Active |
| US11061762B2 | Memory programming techniques | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.