System and method for design based inspection
US10229241B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2018 |
| Grant date | Mar 12, 2019 |
| Priority date | — |
| Expiry date | Aug 20, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F1/84
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Design information related to an irrelevant area of a first layer of semiconductor article may be received. The first layer may be manufactured by illuminating a lithographic mask during a lithographic process. First layer information associated with an outcome or an expected outcome of the illuminating of the lithographic mask during the lithographic process may be received. Information corresponding to a layout of an irrelevant area may be identified in the first layer information. A differentiating attribute that differentiates the layout of the irrelevant area from a layout of a relevant area of the first layer of the semiconductor article may be identified. The differentiating attribute may be used to determine one or more other irrelevant areas of the first layer of the semiconductor article.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.