Method of manufacturing silicon carbide epitaxial wafer
US10229830B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2014 |
| Grant date | Mar 12, 2019 |
| Priority date | — |
| Expiry date | Dec 13, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01B9/02084
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention is aimed at providing a method of manufacturing a silicon carbide epitaxial wafer by which a plurality of silicon carbide epitaxial layers of a predetermined layer thickness can be precisely formed. In the present invention, a first n-type SiC epitaxial layer is formed on an n-type SiC substrate so that the rate of change in impurity concentration between the n-type SiC substrate and the first n-type SiC epitaxial layer will be greater than or equal to 20%. A second n-type SiC epitaxial layer is formed on the first n-type SiC epitaxial layer so that the rate of change in impurity concentration between the first n-type SiC epitaxial layer and the second n-type SiC epitaxial layer will be greater than or equal to 20%.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.