FinFET gate cut after dummy gate removal
US10229854B1 · kind B1 · utility
5Cited by
6References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2017 |
| Grant date | Mar 12, 2019 |
| Priority date | — |
| Expiry date | Dec 14, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices and methods of forming the same include forming dummy gates over a semiconductor fin. An interlayer dielectric is formed around and between the dummy gates. The dummy gates are etched away, leaving gate voids. A first planarizing material is deposited in and over the gate voids. The first planarizing material is removed in a gate cut region. A gate cut plug is deposited in the gate cut region. The remaining first planarizing material is removed to expose the gate voids outside of the gate cut region. A gate stack is formed in the gate voids outside of the gate cut region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.