John R. Sporre
97Patents
9h-index
43Co-inventors
74Inventor score
Filing activity: Jan 24, 2012 → Apr 12, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9608065B1 | Air gap spacer for metal gates | Electricity | 89 | Active |
| US9620590B1 | Nanosheet channel-to-source and drain isolation | Electricity | 86 | Active |
| US9362179B1 | Method to form dual channel semiconductor material fins | Electricity | 24 | Active |
| US9905643B1 | Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors | Electricity | 22 | Active |
| US9721848B1 | Cutting fins and gates in CMOS devices | Electricity | 17 | Active |
| US9741823B1 | Fin cut during replacement gate formation | Electricity | 16 | Active |
| US9450095B1 | Single spacer for complementary metal oxide semiconductor process flow | Electricity | 13 | Active |
| US9318574B2 | Method and structure for enabling high aspect ratio sacrificial gates | Electricity | 11 | Active |
| US9911914B1 | Sub-lithographic magnetic tunnel junctions for magnetic random access memory devices | Electricity | 11 | Active |
| US10074730B2 | Forming stacked nanowire semiconductor device | Electricity | 8 | Active |
| US10014391B2 | Vertical transport field effect transistor with precise gate length definition | Electricity | 8 | Active |
| US9728622B1 | Dummy gate formation using spacer pull down hardmask | Electricity | 7 | Active |
| US10211055B2 | Fin patterns with varying spacing without fin cut | Electricity | 7 | Active |
| US9923080B1 | Gate height control and ILD protection | Electricity | 6 | Active |
| US9842739B2 | Method and structure for enabling high aspect ratio sacrificial gates | Electricity | 6 | Active |
| US9882048B2 | Gate cut on a vertical field effect transistor with a defined-width inorganic mask | Electricity | 5 | Active |
| US9659779B2 | Method and structure for enabling high aspect ratio sacrificial gates | Electricity | 5 | Active |
| US10229854B1 | FinFET gate cut after dummy gate removal | Electricity | 5 | Active |
| US10249533B1 | Method and structure for forming a replacement contact | Electricity | 5 | Active |
| US9536744B1 | Enabling large feature alignment marks with sidewall image transfer patterning | Electricity | 4 | Active |
| US10249738B2 | Nanosheet channel-to-source and drain isolation | Electricity | 4 | Active |
| US10242981B2 | Fin cut during replacement gate formation | Electricity | 4 | Active |
| US9917196B1 | Semiconductor device and method of forming the semiconductor device | Electricity | 4 | Active |
| US10043801B2 | Air gap spacer for metal gates | Electricity | 4 | Active |
| US10381437B2 | Semiconductor device and method of forming the semiconductor device | Electricity | 4 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.