Cryogenic integrated circuit having a heat sink coupled to separate ground planes through differently sized thermal vias
US10229864B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2017 |
| Grant date | Mar 12, 2019 |
| Priority date | — |
| Expiry date | Sep 14, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N69/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit is provided that comprises a thermal sink layer, a first ground plane associated with a first set of circuits that have a first operational temperature requirement, and a first thermally conductive via that couples the first ground plane to the thermal sink layer. The circuit further comprises a second ground plane associated with a second set of circuits that have a second operational temperature requirement that is higher than the first operational temperature requirement, and a second thermally conductive via that couples the second ground plane to the thermal sink layer, wherein the first thermally conductive via has a greater volume of thermal conductive material than the second thermally conductive via to remove heat from the first set of circuits with less gradient than the second set of circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.