Debugging method executed via scan chain for scan test and related circuitry system
US10234503B2 · kind B2 · utility
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10Claims
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Key dates
| Filing date | Dec 20, 2016 |
| Grant date | Mar 19, 2019 |
| Priority date | — |
| Expiry date | Dec 20, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318569
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A circuit debugging method includes: utilizing a debugging circuit to determine an operating status of a specific circuit to generate a result; utilizing a register located in a scan chain path to store the result, wherein the scan chain path is arranged for a scan test; and utilizing an output pad located in the scan chain path to output the result, wherein the result is arranged to be indicative of the operating status of the specific circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.