Semiconductor memory device having detection clock patterns phase-inverted from each other and detection clock generating method thereof
US10236045B2 · kind B2 · utility
3Cited by
20References
19Claims
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Key dates
| Filing date | Mar 14, 2013 |
| Grant date | Mar 19, 2019 |
| Priority date | — |
| Expiry date | Dec 22, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock pattern generating method of a semiconductor memory device is provided. The method includes generating the same clock pattern through a plurality of detection clock output pins when an output selection control signal is in a first state and generating clock patterns different from each other through the plurality of detection clock output pins when the output selection control signal is in a second state different from the first state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.