Seungjun Bae
21Patents
3h-index
30Co-inventors
59Inventor score
Filing activity: Jun 19, 2008 → Oct 24, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8055930B2 | Internal clock signal generating circuits including frequency division and phase control and related methods, systems, and devices | Physics | 24 | Active |
| US7778097B2 | AC coupling circuits including resistive feedback and related methods and devices | Electricity | 8 | Active |
| US7903499B2 | Integrated circuit memory devices including delayed clock inputs for input/output buffers and related systems and methods | Physics | 3 | Active |
| US10236045B2 | Semiconductor memory device having detection clock patterns phase-inverted from each other and detection clock generating method thereof | Physics | 3 | Active |
| US11056158B2 | Memory device and divided clock correction method thereof | Physics | 2 | Active |
| US8391088B2 | Pseudo-open drain type output driver having de-emphasis function, semiconductor memory device, and control method thereof | Physics | 2 | Active |
| US8542036B2 | Transmitter having source follower voltage regulator | Electricity | 2 | Active |
| US11195571B2 | Memory device and method with data input | Physics | 2 | Active |
| US10692561B2 | Semiconductor memory device, memory system, and refresh method thereof | Electricity | 2 | Active |
| US10969420B2 | Test circuits for monitoring NBTI or PBTI | Electricity | 1 | Active |
| US10453504B2 | Memory device and divided clock correction method thereof | Physics | 1 | Active |
| US8026749B2 | Phase locked loop circuit, method of operating phase locked loop circuit and semiconductor memory device including phase locked loop circuit | Electricity | 1 | Active |
| US10666467B2 | Memory device and operation method thereof | Physics | 1 | Active |
| US9355706B2 | Output circuit for implementing high speed data transmition | Physics | 0 | Active |
| US12301236B2 | Equalizer for removing inter symbol interference of data signal by increasing pulse widths of logic low level and logic high level of data signal | Physics | 0 | Active |
| US11862234B2 | Memory device and operation method thereof | Physics | 0 | Active |
| US12154616B2 | Memory device and operation method thereof | Physics | 0 | Active |
| US10593387B2 | Semiconductor memory device and detection clock pattern generating method thereof | Physics | 0 | Active |
| US12394452B2 | ZQ calibration circuit for multiple interfaces | Physics | 0 | Active |
| US10734043B2 | Memory system for adjusting clock frequency | Physics | 0 | Active |
| US10777246B2 | Semiconductor memory device and detection clock pattern generating method thereof | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.