Word line read disturb error reduction through fine grained access counter mechanism
US10236069B2 · kind B2 · utility
1Cited by
6References
12Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 20, 2017 |
| Grant date | Mar 19, 2019 |
| Priority date | — |
| Expiry date | Jun 20, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5644
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus is described. The apparatus includes a storage device having multiple non volatile memory chips and controller circuitry. The controller circuitry is to implement wear leveling of storage cells of the non volatile memory chips at a granularity of segments of storage cell arrays of the non volatile memory chips that share a same disturber node and that are coupled to a same storage cell array wire to diminish disturb errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.