Inventor · Sacramento, CA, US

Robert E. Frickey

13Patents

4h-index

15Co-inventors

49Inventor score

Filing activity: Jul 31, 2009 → Jun 20, 2017

Most-cited inventions

Patent	Title	Area	Cited by	Status
US8332578B2	Method and system to improve the performance of a multi-level cell (MLC) NAND flash memory	Physics	53	Active
US9679658B2	Method and apparatus for reducing read latency for a block erasable non-volatile memory	Physics	13	Active
US9354973B2	Data integrity management in memory systems	Physics	4	Active
US10025535B2	Measurement and reporting of the latency of input and output operations by a solid state drive to a host	Physics	4	Active
US9543019B2	Error corrected pre-read for upper page write in a multi-level cell memory	Physics	2	Active
US10067829B2	Managing redundancy information in a non-volatile memory	Physics	1	Active
US10303571B2	Data recovery in memory devices	Physics	1	Active
US10236069B2	Word line read disturb error reduction through fine grained access counter mechanism	Physics	1	Active
US9183091B2	Configuration information backup in memory systems	Physics	0	Active
US9236136B2	Lower page read for multi-level cell memory	Physics	0	Active
US9524774B2	Lower page read for multi-level cell memory	Physics	0	Active
US9817600B2	Configuration information backup in memory systems	Physics	0	Active
US9552159B2	Configuration information backup in memory systems	Physics	0	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.