Passive components in vias in a stacked integrated circuit package
US10236209B2 · kind B2 · utility
18Cited by
5References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 24, 2014 |
| Grant date | Mar 19, 2019 |
| Priority date | — |
| Expiry date | Dec 24, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Integrated passive component in a stacked integrated circuit package are described. In one embodiment an apparatus has a substrate, a first die coupled to the substrate over the substrate, the first die molding a power supply circuit coupled to the substrate to receive power, a second die having a processing core and coupled to the first die over the first die, the first die being coupled to the power supply circuit to power the processing core, a via through the first die, and a passive device formed in the via of the first die and coupled to the power supply circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.