Error checking and correcting decoder
US10236913B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 2017 |
| Grant date | Mar 19, 2019 |
| Priority date | — |
| Expiry date | May 11, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/617
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An error checking and correcting (ECC) decoder is provided to perform a BCH decoding to decode codeword into decoded data. The ECC decoder includes a syndrome generator circuit, an error locator polynomial circuit, and a decoding circuit. The syndrome generator circuit generates a plurality of syndromes corresponding to the codeword. The error locator polynomial circuit performs an arithmetic operation by using the syndromes to generate a plurality of coefficients in an error locator polynomial. The arithmetic operation includes a plurality of operators, wherein at least one of the operators is a lookup table circuit. The decoding circuit obtains at least one solution to the error locator polynomial with the coefficients and corrects the codeword according to the solution to the error locator polynomial to generate the decoded data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.