No miss cache structure for real-time image transformations with data compression
US10241470B2 · kind B2 · utility
1Cited by
10References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 15, 2018 |
| Grant date | Mar 26, 2019 |
| Priority date | — |
| Expiry date | May 15, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power. The systems and methods can also be adapted to work with compressed image data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.