Inventor · Issaquah, WA, US

Adam J. Muff

115Patents
13h-index
104Co-inventors
85Inventor score

Filing activity: Feb 24, 2005 → Apr 27, 2021

Most-cited inventions

PatentTitleAreaCited byStatus
US8310497B2 Anisotropic texture filtering with texture data prefetching Physics 126 Active
US8217953B2 Anisotropic texture filtering with texture data prefetching Physics 126 Active
US9081501B2 Multi-petascale highly efficient parallel supercomputer Emerging Cross-Sectional Technologies 85 Active
US9978118B1 No miss cache structure for real-time image transformations with data compression Emerging Cross-Sectional Technologies 46 Active
US7809925B2 Processing unit incorporating vectorizable execution unit Physics 45 Active
US8356162B2 Execution unit with data dependent conditional write instructions Physics 44 Active
US8082420B2 Method and apparatus for executing instructions Physics 38 Active
US7814303B2 Execution of a sequence of vector instructions preceded by a swizzle sequence instruction specifying data element shuffle orders respectively Physics 24 Active
US9971713B2 Multi-petascale highly efficient parallel supercomputer Emerging Cross-Sectional Technologies 22 Active
US8751830B2 Memory address translation-based data encryption/compression Physics 16 Active
US7783860B2 Load misaligned vector with permute and mask insert Physics 14 Active
US9256428B2 Load latency speculation in an out-of-order computer processor Physics 14 Active
US9147078B2 Instruction set architecture with secure clear instructions for protecting processing unit architected state information Physics 13 Active
US9292290B2 Instruction set architecture with opcode lookup using memory attribute Physics 13 Active
US7890699B2 Processing unit incorporating L1 cache bypass Physics 12 Active
US8332452B2 Single precision vector dot product with “word” vector write mask Physics 11 Active
US8930432B2 Floating point execution unit with fixed point functionality Physics 10 Active
US7873066B2 Streaming direct inter-thread communication buffer packets that support hardware controlled arbitrary vector operand alignment in a densely threaded network on a chip Physics 8 Active
US8412760B2 Dynamic range adjusting floating point execution unit Physics 8 Active
US7926009B2 Dual independent and shared resource vector execution units with shared register file Physics 8 Active
US9032191B2 Virtualization support for branch prediction logic enable / disable at hypervisor and guest operating system levels Physics 7 Active
US7234017B2 Computer system architecture for a processor connected to a high speed bus transceiver Physics 7 Expired
US9183399B2 Instruction set architecture with secure clear instructions for protecting processing unit architected state information Physics 7 Active
US8954755B2 Memory address translation-based data encryption with integrated encryption engine Physics 7 Active
US8935694B2 System and method for selectively saving and restoring state of branch prediction logic through separate hypervisor-mode and guest-mode and/or user-mode instructions Physics 6 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.