Replay reduction by wakeup suppression using early miss indication
US10241797B2 · kind B2 · utility
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6Claims
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Key dates
| Filing date | Jul 17, 2012 |
| Grant date | Mar 26, 2019 |
| Priority date | — |
| Expiry date | Jul 20, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for reducing a number of operations replayed in a processor includes decoding an operation to determine a memory address and a command in the operation. If data is not in a way predictor based on the memory address, a suppress wakeup signal is sent to an operation scheduler, and the operation scheduler suppresses waking up other operations that are dependent on the data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.