Configurable I/O address translation data structure
US10241923B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2012 |
| Grant date | Mar 26, 2019 |
| Priority date | — |
| Expiry date | Mar 17, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2206/1004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In response to a determination to allocate additional storage, within a real address space employed by a system memory of a data processing system, for translation control entries (TCEs) that translate addresses from an input/output (I/O) address space to the real address space, a determination is made whether or not a first real address range contiguous with an existing TCE data structure is available for allocation. In response to determining that the first real address range is available for allocation, the first real address range is allocated for storage of TCEs, and a number of levels in the TCE data structure is retained. In response to determining that the first real address range is not available for allocation, a second real address range discontiguous with the existing TCE data structure is allocated for storage of the TCEs, and a number of levels in the TCE data structure is increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.