No miss cache structure for real-time image transformations
US10242654B2 · kind B2 · utility
3Cited by
18References
19Claims
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Key dates
| Filing date | Jan 25, 2017 |
| Grant date | Mar 26, 2019 |
| Priority date | — |
| Expiry date | Jan 25, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.