Dual sensing current latched sense amplifier
US10242720B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2010 |
| Grant date | Mar 26, 2019 |
| Priority date | — |
| Expiry date | Jun 4, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sense amplifier and method thereof are provided. The sense amplifier includes first and second transistors coupled to first and second bit lines, respectively. The first and second transistors are configured to connect the first and second bit lines to a differential amplifier during a first state (e.g., when a differential voltage is present on the first and second bit lines and prior to a sense signal transition) and to isolate the first and second bit lines from the differential amplifier during a second state (e.g., after the sense signal transition). The sense amplifier further includes a third transistor configured to deactivate the differential amplifier during the first state and configured to activate the differential amplifier during the second state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.