Ritu Chaba
21Patents
6h-index
22Co-inventors
65Inventor score
Filing activity: Dec 21, 2007 → Jan 7, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7881137B2 | Read assist for memory circuits with different precharge voltage levels for bit line pair | Physics | 19 | Active |
| US9030863B2 | Read/write assist for memories | Electricity | 14 | Active |
| US7710183B2 | CMOS level shifter circuit design | Electricity | 12 | Active |
| US8223567B2 | Memory read stability using selective precharge | Physics | 11 | Active |
| US9418716B1 | Word line and bit line tracking across diverse power domains | Physics | 11 | Active |
| US8183713B2 | System and method of providing power using switching circuits | Electricity | 7 | Active |
| US9524972B2 | Metal layers for a three-port bit cell | Electricity | 6 | Active |
| US7884645B2 | Voltage level shifting circuit and method | Electricity | 6 | Active |
| US9082465B2 | Weak keeper circuit for memory device | Physics | 4 | Active |
| US10242720B2 | Dual sensing current latched sense amplifier | Physics | 4 | Active |
| US9514805B1 | Intelligent bit line precharge for improved dynamic power | Physics | 2 | Active |
| US8760953B2 | Sense amplifier with selectively powered inverter | Physics | 1 | Active |
| US10622044B2 | Memory hold margin characterization and correction circuit | Electricity | 1 | Active |
| US9188642B2 | Reconfigurable memory interface circuit to support a built-in memory scan chain | Physics | 1 | Active |
| US10923185B2 | SRAM with burst mode operation | Physics | 1 | Active |
| US9111589B2 | Memory timing circuit | Physics | 0 | Active |
| US9916904B2 | Reducing leakage current in a memory device | Physics | 0 | Active |
| US8929153B1 | Memory with multiple word line design | Physics | 0 | Active |
| US10290345B2 | Intelligent bit line precharge for improved dynamic power | Physics | 0 | Active |
| US11527282B2 | SRAM with burst mode operation | Physics | 0 | Active |
| US10141317B2 | Metal layers for a three-port bit cell | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.