Method and apparatus for background memory subsystem calibration
US10242723B1 · kind B1 · utility
5Cited by
9References
20Claims
0Family size
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Key dates
| Filing date | Dec 19, 2017 |
| Grant date | Mar 26, 2019 |
| Priority date | — |
| Expiry date | Dec 19, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for performing a background calibration in a memory subsystem is disclosed. A memory subsystem includes a memory controller coupled to a memory. The memory controller is coupled to receive data during reads from the memory on a functional data path and a duplicate data path. The memory controller further includes calibration circuitry. During reads of data conducted during normal operation, the calibration circuit calibrates a first delay locked loop (DLL) in the duplicate data path. A second DLL, in the functional data path, may be adjusted based on the calibrations conducted in the duplicate data path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.