Memory device for controlling refresh operation by using cell characteristic flags
US10242731B2 · kind B2 · utility
1Cited by
14References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 2, 2015 |
| Grant date | Mar 26, 2019 |
| Priority date | — |
| Expiry date | Dec 14, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4061
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory cell array that includes a plurality of memory cell rows; and a refresh address generator configured to store flags respectively corresponding to the plurality of memory cell rows, generate refresh row addresses respectively corresponding to the plurality of memory cell rows by performing a count operation, and according to the flags, change a refresh period of the plurality of memory cell rows.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.