Je-Min Ryu
23Patents
5h-index
35Co-inventors
65Inventor score
Filing activity: May 2, 2012 → Mar 2, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10083722B2 | Memory device for performing internal process and operating method thereof | Electricity | 11 | Active |
| US8804448B2 | Method of selecting anti-fuses and method of monitoring anti-fuses | Physics | 9 | Active |
| US10592467B2 | Semiconductor memory device and method of operating a semiconductor device in a processor mode or a normal mode | Physics | 9 | Active |
| US10410685B2 | Memory device for performing internal process and operating method thereof | Electricity | 6 | Active |
| US11010316B2 | Memory device for adjusting memory capacity per channel and memory system including the same | Physics | 5 | Active |
| US11295808B2 | Memory device transmitting and receiving data at high speed and low power | Physics | 4 | Active |
| US10224114B2 | Semiconductor device using a parallel bit operation and method of operating the same | Physics | 3 | Active |
| US10319451B2 | Semiconductor device having chip ID generation circuit | Physics | 3 | Active |
| US9287009B2 | Repair circuit and fuse circuit | Physics | 3 | Active |
| US10262699B2 | Memory device for performing internal process and operating method thereof | Electricity | 3 | Active |
| US10768824B2 | Stacked memory device and a memory chip including the same | Emerging Cross-Sectional Technologies | 1 | Active |
| US9601216B2 | Semiconductor device including redundancy cell array | Physics | 1 | Active |
| US9343175B2 | Fuse data reading circuit having multiple reading modes and related devices, systems and methods | Physics | 1 | Active |
| US10331354B2 | Stacked memory device and a memory chip including the same | Emerging Cross-Sectional Technologies | 1 | Active |
| US10242731B2 | Memory device for controlling refresh operation by using cell characteristic flags | Physics | 1 | Active |
| US10468092B2 | Memory device for controlling refresh operation by using cell characteristic flags | Physics | 1 | Active |
| US8897055B2 | Memory device, method of operating the same, and electronic device having the memory device | Physics | 1 | Active |
| US9123407B2 | Devices and methods for deciding data read start | Physics | 1 | Active |
| US10671464B2 | Memory device comprising status circuit and operating method thereof | Physics | 0 | Active |
| US11239210B2 | Semiconductor die for determining load of through silicon via and semiconductor device including the same | Electricity | 0 | Active |
| US11836097B2 | Memory device for adjusting memory capacity per channel and memory system including the same | Physics | 0 | Active |
| US11769547B2 | Memory device transmitting and receiving data at high speed and low power | Physics | 0 | Active |
| US10916525B2 | Semiconductor die for determining load of through silicon via and semiconductor device including the same | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.