Low voltage difference operated EEPROM and operating method thereof
US10242741B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2017 |
| Grant date | Mar 26, 2019 |
| Priority date | — |
| Expiry date | Nov 17, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/681
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a low voltage difference-operated EEPROM and an operating method thereof wherein at least one transistor structure is formed in a semiconductor substrate and each includes a first electric-conduction gate. An ion implantation is performed by masking partial regions to prevent the existence of the conventional lightly doped drain (LDD) structure. An undoped region is formed in the semiconductor substrate under the two sides of the first electric-conductive gate, to increase the intensity of electric field between the gate and the substrate or between the gate and the transistor, whereby to reduce the voltage differences required for writing and erasing. The present invention also discloses an operating method for the low voltage difference-operated EEPROM. The present invention applies to the EEPROM with a single gate transistor structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.